HLASM - BLR = Branch on Low Register

The opcode of the BLR extended mnemonic is X'07' with mask B'0100'.

The mask is the third hex digit of the instruction, and - though this is uncommon - can be regarded as the third hex digit of the opcode as well.

Usage

  1. Perform a branch if the condition code is 1 or B'01', meaning "low"
  2. Condition code 1 may occur after compare operations, such as CLC, indicating the first operand was lower than the second.

Arguments

  1. Register holding the destination address.

Function

  1. The processor uses the PSW's two-bit condition code as an index into the 4-bit condition mask.
  2. If the selected mask-bit is one, then it branches to the address specified in the second argument. If the bit is zero, then the processor continues with the next instruction.
  3. The condition code does not change.

Special Cases

  1. If the destination address is in register 0 no branch will be taken.

Related Instructions

  1. BMR is a synonym for the BLR mnemonic.
  2. BL branches to a location that is directly addressable in base-displacement form.
  3. BCR is the real instruction associated with this extended mnemonic.

Hardware

  1. All hardware supports the BLR instruction.

Remarks

  1. The PSW's Amode setting determines how many bits are used for the destination address.

Examples

         YREGS                          * Define register names
         ...
         CR    R1,R6                    * Limit reached?
         BLR   R14                      * No: return to caller
         ...

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